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    Projects > ELECTRONICS > 2017 > > VLSI

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    ELECTRONICS

    SL.NO CODE TITLE Domain LANGUAGE
    1 HSE17V086 Algorithm and Architecture Design of Adaptive Filters with Error Nonlinearities VLSI VHDL / VERILOG
    2 HSE17V087 A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA VLSI VHDL / VERILOG
    3 HSE17V088 An Efficient O(N) Comparison-Free Sorting Algorithm VLSI VHDL / VERILOG
    4 HSE17V089 Approximate Error Detection with Stochastic Checkers VLSI VHDL / VERILOG
    5 HSE17V090 Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation VLSI VHDL / VERILOG
    6 HSE17V091 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding VLSI VHDL / VERILOG
    7 HSE17V092 Deep Convolutional Neural Network Architecture with Reconfigurable Computation Patterns. VLSI VHDL / VERILOG
    8 HSE17V093 Preweighted Linearized VCO Analog-to-Digital Converter VLSI VHDL / VERILOG
    9 HSE17V094 Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT VLSI VHDL / VERILOG
    10 HSE17V095 Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations VLSI VHDL / VERILOG
    11 HSE17V096 Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device VLSI VHDL / VERILOG
    12 HSE17V097 Energy-Efficient Object Detection Using Semantic Decomposition VLSI VHDL / VERILOG
    13 HSE17V098 Excavating the Hidden Parallelism Inside DRAM Architectures with Buffered Compare VLSI VHDL / VERILOG
    14 HSE17V099 Fast Stochastic Analysis of Electro migration in Power Distribution Networks VLSI VHDL / VERILOG
    15 HSE17V100 On the Implementation of Computation-in-Memory Parallel Adder VLSI VHDL / VERILOG
    16 HSE17V101 Overloaded CDMA Crossbar for Network-On-Chip VLSI VHDL / VERILOG
    17 HSE17V102 Security-Adaptive Voltage Conversion as a Lightweight Countermeasure Against LPA Attacks VLSI VHDL / VERILOG
    18 HSE17V103 Selecting Replacements for Undetectable Path Delay Faults VLSI VHDL / VERILOG
    19 HSE17V104 Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing VLSI VHDL / VERILOG
    20 HSE17V105 Two-Extra-Column Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes VLSI VHDL / VERILOG